#define APLL_LOCK 	*((volatile unsigned long*)0x7E00F000)
#define MPLL_LOCK 	*((volatile unsigned long*)0x7E00F004)
#define EPLL_LOCK 	*((volatile unsigned long*)0x7E00F008)
#define APLL_CON 	*((volatile unsigned long*)0x7E00F00C)
#define MPLL_CON 	*((volatile unsigned long*)0x7E00F010)
#define EPLL_CON0 	*((volatile unsigned long*)0x7E00F014)
#define EPLL_CON1 	*((volatile unsigned long*)0x7E00F018)
#define CLK_SRC		*((volatile unsigned long*)0x7E00F01C)

#define OTHERS		*((volatile unsigned long*)0x7E00F900)


#define CLK_DIV0		*((volatile unsigned long*)0x7E00F020)
#define ARM_RATIO		0
#define HCLKX2_RATIO	1
#define HCLK_RATIO		1
#define PCLK_RATIO		3
#define MPLL_RATIO		0

void clock_init(void)
{
	APLL_LOCK = 0xFFFF;		//设置lock time,系统默认值
	MPLL_LOCK = 0xFFFF;
	EPLL_LOCK = 0xFFFF;

	OTHERS &= ~(0xC0);		//当CPU时钟 != HCLK 时，须设置为异步模式
	while(OTHERS & 0x0F00);		//等待进入异步模式

	CLK_DIV0 = (ARM_RATIO<<0) | (MPLL_RATIO<<4) | (HCLK_RATIO<<8) | (HCLKX2_RATIO) | (PCLK_RATIO<<12);		//设置系统分频
	
	/*配置PLL时钟*/
	APLL_CON = (0x01<<31) | (266<<16) | (3<<8) | (1<<0);	//FOUT:532MHz MDIV:266 PDIV:3 SDIV:1
	MPLL_CON = (0x01<<31) | (266<<16) | (3<<8) | (1<<0);	//FOUT:532MHz MDIV:266 PDIV:3 SDIV:1

	CLK_SRC = 0x03;	//0:APLL_SEL 1:MPLL_SEL 
}
